DSP TU Part 3

This is part 3 of the DSP terminal unit project. Part 1 was a proof of concept using a PIC32MZ evaluation board. Part 2 is the initial PCB design and further firmware development. The revisions are:

• Rev A - Original version. Display connector is backwards, so the display has to be hand wired instead of just plugging it in. Otherwise, the board is good.
• Rev B - Fixes the display connector, adds test points, and resizes the board to fit an extruded aluminum case.
• Rev C - Changes board outline and mounting holes so the board can fit in a plastic case.

The enclosure is a Heyiarbeit DFC3500GP0402. There are 12 plastic spacers molded into the bottom of the case. The PCB is mounted using three of these spacers. Some of the spacers interfere with the leads of through hole parts protruding from the board. These spacers can be cut off with diagonal cutters. The PCB is mounted to the bottom of the enclosure using three M3 x 6 pan head Phillips screws with a 0.50 pitch.

Loop Debounce

It was noted that the software UART driving the terminal (DSP TU in modem mode) showed errors on loop keyboard data. In my case, this is especially the case for the model 14 TD. The TD needs cleaning and adjustment.A test was run to determine the loop current where U4, the H11AA1, output transitioned from mark to space to make sure the loop detection was not overly sensitive. Measurements indicate the transition is at 27 mA, which is about where it should be (half the 60 mA loop current).

Keyboards on the loop often have some contact bounce that can false the software UART. That contact bounce also drove the AFSK generator. The software UART does not see this bounce on received signals since the tone filters reduce the high frequency sidebands generated by the bounce.

To reduce bounce, a biquad low pass filter was added. When the loop sense indicates mark, the LPF is fed with 1.0. When a space is sensed, the LPF is fed with -1.0. The output of the LPF is then compared with 0.0. If higher than 0.0, a mark is sent to the AFSK generator and the software UART. If the LPF output is less than or equal to 0.0, a space is sent to the AFSK generator and software UART. The default cutoff frequency for the LPF is 0.5 times the baud rate.

Images on the right show the output of the LPF with the baud rate multiplier of 20 and with a multiplier of 0.5. With the cutoff set at 0.5*BR, the LPF output gets to 1.0 at the end of the bit time. The output crosses the 0.0 threshold half way through a bit time. The result is suppression of contact bounce and a 1/2 bit delay. Note that the DDS AFSK generator still switches between the mark and space frequencies instead of smoothly transitioning as it would if the DDS were directly driven by the LPF. If we were to slowly transition between mark and space (using the LPF), the LPF would be "in series" with the tone filters on the receive end further attenuating the sidebands. It's an interesting question as to where the bandwidth limiting should be. At this point, the only limiting on the transmit side is due to the relatively low sample rate (8 kHz) of the DDS, the 4 kHz LPF on the AFSK output, and bandwidth limits in the transmitter. On the receive side, the tone filter bandwidth is 1.7 times the baud rate. This allows the discriminator voltage to reach full amplitude while keeping the filter bandwidth low to reduce noise.

Bootloadabe Firmware v 251024 DspTuBootloadable251024.hex

Parts List

• Main PCB
  • KiCAD Files
  • Bare or Stuffed Board from PCBWAY - On the right side of the page, choose bare board or assembled.
  • Digikey List
• Heyiarbeit DFC3500GP0402

Firmware Updates

References

• DSP TU - Proof of concept on Microchtip evaluation board
• DSP TU 2 - PCB and firmware development
• Schematic, rev C